The present invention generally relates to semiconductor wafer fabrication, and more particularly to a semiconductor wafer having a decreased degree of misalignment errors and a method for decreasing the degree of misalignment errors.
For more than a decade, rapid thermal process (RTP) reactors have been utilized in the processing of semiconductor wafers. RTP reactors have a process cycle which takes considerably less time than conventional reactors. For example, while conventional reactors may require forty to ninety minutes to perform a particular processing function on wafers, RTP reactors need only two to fifteen minutes to accomplish the same processing function.
A problem associated with RTP reactors is that high temperature gradients are created across the wafers-in-process, leading to thermal stress which leads to plastic deformation of the wafers-in-process, particularly in unpatterned and unprocessed areas at the edges of the wafers-in-process. Plastic deformation in turn may cause photolithography pattern misregistration because alignment marks for lithographic pattern registration are typically provided at the edges of wafers. If these alignment marks are distorted, due to wafer distortion, misalignment of the photolithograph step from one wafer layer to another may occur, causing device failure as device features are misaligned from one wafer layer relative to another.
For example, a stepper mechanism prints patterns on a photoresist layer of a wafer-in-process in sequence, moving a predetermined distance from one area of the wafer-in-process to another for each printing operation. The stepper continues this process until an entire layer of die patternings have been printed across the surface of the substrate. The stepper uses global alignment marks, also called combis, to ascertain its position above the wafer-in-process to determine where each die pattern is to be printed on a layer of photoresist. If the wafer-in-process has distortions in the combi sites, the unpatterned and unfabricated areas containing the combis which are typically at the unpatterned wafer periphery, the printing of the photoresist may be misaligned from where actual printing should occur. Thus, since the global alignment marks have moved due to wafer distortion, the stepper may print the next layer of photoresist misaligned relative to the previous layer, creating fabrication misregistrations between the layers.
Wafer distortions occurring at the periphery of wafers-in-process where the alignment marks are located are difficult to correct using conventional methods due to the random nature of such distortions. Specifically, with reference to FIGS. 1-4, the misalignments found at the periphery of a wafer due to distortion often do not conform, either in magnitude or phase, to the misalignments which may occur at the wafer""s center. FIG. 1 illustrates raw grid data from the wafer""s center, while FIG. 2 shows non-correctable grid data from the wafer""s center. FIGS. 3 and 4 respectively illustrate the raw and non-correctable grid data from the wafer""s periphery. It should be noted that while the misalignments in the wafer""s center can be virtually completely corrected in the stepper device, a majority of the misalignments were retained along the wafer""s periphery where the alignment marks are located. The retained misalignments as they relate to the global alignment marks will lead to a misregistration with the next patterning layer when the stepper uses the alignment marks for pattern printing.
Referring to FIG. 5, a patterned wafer 10 is shown with patterned portions 14 and non-patterned portions 13. Some of the nonpatterned portions 13 serve as global alignment mark sites, also called combi sites, 12. As illustrated, four combi sites 12 are positioned about the periphery of the wafer 10, each separated from adjacent sites 12 by generally ninety degrees and offset from x- and y-axes. FIG. 6 shows a patterned wafer 20 having patterned portions 24 and non-patterned portions 23. As with wafer 10, some of the non-patterned portions 23 serve as combi sites 22. The four illustrated combi sites 22 are located on the x- or y-axes. Both wafers 10 and 20 show conventional patterning and locations of combi sites 12, 22 on the periphery of the wafers. Each of the wafers 10, 20 experience thermal stress-induced misalignments at the unpatterned combi sites which may make it difficult for a lithographic patterning device, such as a stepper, to correctly pattern a photoresist layer.
Accordingly, a technique is needed to lessen peripheral distortions at combi sites due to thermally-induced stresses to thereby diminish registration errors in semiconductor fabrication processes.
The present invention provides a semiconductor wafer that includes a substrate, one or more mask patterns located on the substrate, and one or more global alignment sites, each of the sites including an mask pattern partially overlying the site and not overlying a global alignment mark.
The present invention also provides a method for diminishing misalignments on a periphery of semiconductor wafers. The method includes the steps of determining the locations of global alignment marks on a wafer, determining the optimal size of partial fields to minimize nonpatterned areas adjacent to the global alignment marks, printing the partial fields at each masking layer during exposure of a photoresist material, and developing the photoresist material and processing the wafer at each mask layer.
The foregoing and other advantages and features of the invention will be more readily understood from the following detailed description of preferred embodiments, which is provided in connection with the accompanying drawings.